We are looking for an FPGA Engineer to join our team and work on high-performance FPGA/SoC solutions, with a strong focus on digital signal processing (DSP), algorithms, and RF applications.

Location

This is a full-time, hybrid role based in Tallinn, Estonia.

Responsibilities

• Design and develop FPGA/SoC solutions based on Xilinx 7-Series and UltraScale/UltraScale+ devices.
• Develop RTL designs using VHDL and Verilog.
• Implement and optimize DSP algorithms, including FIR/IIR filters, FFT, DDC/DUC, decimation/interpolation, mixers, NCOs, and other signal-processing blocks.
• Develop digital signal-processing chains for RF / SDR systems.
• Work with high-speed data paths and streaming architectures.
• Integrate FPGA logic with Xilinx SoC and embedded processor subsystems.
• Perform RTL simulation, verification, and hardware debugging.
• Optimize FPGA designs for timing closure, resource utilization, and performance.
• Work with Xilinx Vivado, synthesis, implementation, constraints, and Xilinx IP cores.
• Analyze and resolve timing, clock-domain, and hardware-related issues.
• Collaborate with hardware, embedded software, DSP, and RF engineers.

Requirements
 

• 5+ years of commercial experience in FPGA development.
• Strong knowledge of VHDL and/or Verilog; experience with both is a plus.
• Hands-on experience with Xilinx FPGA/SoC platforms, including:
  • 7-Series;
  • UltraScale / UltraScale+;
  • Zynq SoC.
• Solid understanding of digital design and RTL development.
• Practical experience implementing DSP algorithms on FPGAs.
• Understanding of RF signal processing and SDR architectures.
• Experience with Xilinx Vivado and Xilinx IP.
• Good understanding of timing analysis, clock-domain crossing (CDC), reset strategies, and FPGA constraints.
• Experience debugging FPGA designs on real hardware.

Nice to Have

• Experience with Zynq-7000 / Zynq UltraScale+ MPSoC.
• Knowledge of AXI4 / AXI-Stream.
• Experience with high-speed interfaces such as JESD204, Ethernet, PCIe, DDR, etc.
• Experience implementing FFT, DDC/DUC, channelizers, beamforming, and other DSP blocks.
• Experience with ADC/DAC interfaces and RF transceivers.
• Knowledge of SystemVerilog, Tcl, Python, or C/C++.
• Experience with hardware/software co-design.
• Strong understanding of fixed-point arithmetic and FPGA-oriented DSP optimization.